This invention relates generally to digital circuitry, and more particularly to logic level shifters for digital circuitry.
Portable computers are becoming very popular because they are easy to transport, can be used virtually anywhere, and because they are approaching the computing power of their desk-top brethren. Portable computers are also becoming smaller and lighter in weight, which generally means that the batteries which power them are also becoming smaller. As a result, the new generation of small, light, but powerful portable computers require low-power, yet high speed, circuitry.
Because portable computers are usually battery powered, it is very important that they draw as little power as possible. In consequence, the circuitry of virtually all portable computers is implemented in complementary metal oxide semiconductor (CMOS) technology, which is noted for its low power requirements. Also, the microprocessor or controller at the heart of the portable computer often operates internally on a lower voltage than the rest of the computer's circuitry to reduce its static power consumption. Unfortunately, lowering the voltage also reduces the speed at which the microprocessor or controller operates, which means that other portions of the circuitry must not unduly add to the delay of signals being produced by the microprocessor or controller.
In FIG. 1, a microprocessor or controller 10 can utilize an internal or "core" operating voltage of three volts d.c. but must drive external or "ring" logic at standard ISA (Industry Standard Architecture) voltages of about five volts d.c. This requires a logic level shifter 12 which couples the core logic to a pad driver 14 and, from there, to a lead 16 of the microprocessor or controller 10. The logic level shifter 12 must be capable providing sufficient current to the pad driver 14. The pad driver 14 usually drives a capacitive load C.sub.L of about 200 picofarads.
A prior art logic level shifter 12' is illustrated in FIG. 2. The channel of a p-channel metal oxide field effect transistor (MOSFET) 18 and the channel of a n-channel MOSFET 20 are coupled together in a typical series CMOS configuration between a source of the ring voltage Vr and ground. The gates of the MOSFETS 18 and 20 are coupled to the input of the logic level shifter 12', and the node 22 between the channels of the MOSFETS is coupled to the pad driver 14. Typically, the relative size of the MOSFETS are selected so that the trip point between a logic 0 and a logic 1 are skewed towards the lower end of a voltage range. For example, if the voltage range is 0-3 volts, the trip point would be made less than 1.5 volts, while if the voltage range is 0-5 volts, the trip point would be made less than 2.5 volts. This skewing of the trip point enables the input signal "IN" to have a swing of 0 to 3 volts while generating an output signal that has a swing of 0 to 5 volts.
A problem with the prior art logic level shifter 12' of FIG. 2 is that it exhibits a relatively high static current. For example, when the input signal IN is at 3 volts, the output will be at 0 volts because the n-channel MOSFET 20 is on, but the p-channel MOSFET will not be shut entirely off. Therefore, current will flow from Vr to ground through MOSFETS 18 and 20. In consequence, there is a considerable static current drain through the level shifter 12', which can quickly deplete the batteries of a portable computer.